MT46V16M8-5 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT46V16M8-5 Datasheet PDF : 9 Pages
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READ LATENCY
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
should be set to 3 clocks, as shown in the CAS Latency
Diagram and Mode Register Definition Diagram.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
CK#
CK
COMMAND
DQS
DQ
CAS Latency
Diagram
T0
T1
T2 T2n
T3 T3n
READ
NOP
NOP
NOP
CL = 3
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
TRANSITIONING DATA
DON’T CARE
PREVIEW
128Mb: x8
DDR400 SDRAM Addendum
Mode Register Definition
Diagram
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register (Mx)
0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
Reserved
3
Reserved
Reserved
Reserved
Reserved
M11 M10 M9 M8 M7
0 0 0 00
0 0 0 10
- - - --
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
128Mb: x8DDR400 SDRAM
128Mbx8DDR400.p65 – Rev. A (1/30/02-B)
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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