TQFP Pin Description
Symbol
Type
A0, A1
I
A2–A17
I
A18
I
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
I/O
DQD1–DQD9
NC
—
BW
I
BA, BB, BC, BD
I
NC
—
CK
I
GW
I
E2
I
E1
I
G
I
ADV
I
ADSP, ADSC
I
ZZ
I
LBO
I
VDD
I
VSS
I
VDDQ
I
GS881E18B(T/D)/GS881E32B(D)/GS881E36B(T/D)
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Input
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ Data I/Os; active low
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active high
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.00b 12/2002
4/34
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.