H83022 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

H83022

16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Renesas Electronics 

Appendix D. Pin States

Reset in T3 State: Figure D.3 is a timing diagram for the case in which RES goes low during the

T3 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to

the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The

address bus outputs are held during the T3 state.The same timing applies when a reset occurs in the

T2 state of an access cycle to a two-state-access area.

Access to external address

T1

T2

T3

φ

RES

Internal

reset signal

Address bus

(modes 1, 3, 5, 6)

AS (modes 1, 3, 5, 6)

H'000000

RD (read access)

(modes 1, 3, 5, 6)

WR (write access)

(modes 1, 3, 5, 6)

Data bus

(write access)

(modes 1, 3, 5, 6)

I/O port

(modes 1, 3, 5 to 7)

High impedance

High impedance

Figure D.3 Reset during Memory Access (Reset during T3 State)

Rev.2.00 Mar. 22, 2007 Page 677 of 684

REJ09B0352-0200

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