Philips Semiconductors
8-bit static shift register
Product specification
HEF4021B
MSI
FUNCTION TABLES
Serial operation
INPUTS
n
CP
DS
PL
1
D1
L
2
D2
L
3
D3
L
6
X
L
7
X
L
8
X
L
X
L
OUTPUTS
O5
O6
O7
X
X
X
X
X
X
X
X
X
D1
X
X
D2
D1
X
D3
D2
D1
no change
Parallel operation
INPUTS
OUTPUTS
n
CP
DS
PL
O5
O6
O7
X
X
H
P5
P6
P7
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
Dn = either HIGH or LOW
n = number of clock pulse transitions
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → On
HIGH to LOW
LOW to HIGH
PL → On
HIGH to LOW
LOW to HIGH
Output transition
times
HIGH to LOW
LOW to HIGH
5
10 tPHL
15
5
10 tPLH
15
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
125
250 ns
55
110 ns
40
80 ns
115
230 ns
50
100 ns
40
80 ns
120
240 ns
55
110 ns
40
80 ns
105
210 ns
50
100 ns
40
80 ns
60
120 ns
30
60 ns
20
40 ns
60
120 ns
30
60 ns
20
40 ns
TYPICAL EXTRAPOLATION
FORMULA
98 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
88 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
93 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
January 1995
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