HMP8115CN View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

HMP8115CN

NTSC/PAL Video Decoder

Intersil 

HMP8115

Electrical Specifications

PARAMETER

VCC = VAA = 5.0V, TA = 25oC (Continued)

SYMBOL

TEST CONDITION

MIN

TYP

MAX UNITS

Video Input Bandwidth

BW

1VP-P Sine Wave Input to

5

-

-

MHz

-3dBc Reduction, (Note 43)

ADC Input Range

ADC Integral Nonlinearity

AIN FULL SCALE

AIN OFFSET

INL

Best Fit Linearity

-

1

-

VP-P

-

1.5

-

V

-

2

-

LSB

ADC Differential Nonlinearity

DNL

-

0.35

-

LSB

VIDEO PERFORMANCE

Differential Gain

Differential Phase

Hue Accuracy

Color Saturation Accuracy

Luminance Nonlinearity

DG

Modulated Ramp (Note 43)

-

2

-

%

DP

-

1

-

Deg.

75% Color Bars (Note 43)

-

2

-

Deg.

-

2

-

%

NTC-7 Composite (Note 43)

-

2

-

%

SNR

GENLOCK PERFORMANCE

SNRL WEIGHTED Pedestal Input (Note 43)

-

50

-

dB

Horizontal Locking Time

tLOCK

Time from Initial Lock

Acquisition to an Error of

1 Pixel. (Note 43)

2

3

-

Fields

Long-Term horizontal Sync

Lock Range

Range over specified pixel jitter

-

-

is maintained. Assumes line

time changes by amount indicat-

ed slowly between over one

field. (Note 43)

5

%

Number of Missing Horizontal

Syncs Before Lost Lock Declared

HSYNC LOST

Programmable via register 04H 1 or 12

(Note 43)

1 or 12

1 or 12 Hsyncs

Number of Missing Vertical Syncs

Before Lost Lock Declared

VSYNC LOST

1 or 3

1 or 3

1 or 3 Vsyncs

Long-Term Color Subcarrier

Lock Range

Range over color subcarrier

-

locking time and accuracy spec-

ifications are maintained. Sub-

carrier frequency changes by

amount indicated slowly over 24

hours. (Note 43)

±200

±400

Hz

Vertical Sample Alignment

(Notes 43, 45)

-

1/8

-

Pixel

-

10

-

ns

NOTES:

43. Guaranteed by design or characterization.

44. Test performed with CL = 40pF, IOL = 4mA, IOH = -4mA. Input reference level is 1.5V for all inputs. VIH = 3.0V, VIL = 0V.

45. This should not be confused with Clock Jitter, since the HMP8115 does not generate the sample clock. Thus, clock jitter is solely depen-

dent on the source of the CLK2 signal. The Vertical Sample Alignment parameter specifies how accurately samples align vertically from

one scan line to the next.

42

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