HYS72D128300GBR-5-B View Datasheet(PDF) - Infineon Technologies
Part Name
Description
Manufacturer
HYS72D128300GBR-5-B Datasheet PDF : 45 Pages
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HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Pin Configuration
Table 4 Pin Configuration1) (cont’d)
PIN#
Symbol
PIN#
Symbol
PIN#
42
VSS
43
A1
44
CB0
88
DQ59
135
89
VSS
136
90
NC
137
45
CB1
91
SDA
138
46
VDD
92
SCL
139
47
DQS8
93
VSS
140
1) A12 is used for 256Mbit and 512Mbit based modules only.
Symbol
CB5
VDDQ
CK0
CK0
VSS
DQS17
PIN#
181
182
183
184
–
–
Symbol
SA0
SA1
SA2
VDDSPD
–
–
Table 5 Address Format
Density Organization Memory
Ranks
1 GB 128M x 72
1
1 GB 128M x 72
2
2 GB 256M x 72
2
SDRAMs # of
SDRAMs
128M × 4 18
64M × 8 18
128M × 4 36
# of row/bank/
column bits
13/2/12
13/2/11
13/2/12
Refresh Period Interval
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
8K
64 ms 7.8 µs
Data Sheet
10
Rev. 0.5, 2003-12
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