IDT70121S45JG View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT70121S45JG

HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

Integrated Device Technology 

IDT70121/IDT70125

High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)

tRC

ADDRESS

tAA

tOH

tOH

DATAOUT

BUSYOUT

PREVIOUS DATA VALID

DATA VALID

tBDD(3,4)

2654 drw 05

Timing Waveform of Read Cycle No. 2, Either Side(5)

tACE

CE

tAOE (4)

tHZ (2)

OE

tLZ (1)

tHZ (2)

DATAOUT

ICC

CURRENT

ISS

tLZ (1)

tPU

50%

VALID DATA

tPD (4)

50%

2654 drw 06

NOTES:

1. Timing depends on which signal is aserted last, OE or CE.

2. Timing depends on which signal is deaserted first, OE or CE.

3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations

BUSY has no relationship to valid output data.

4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.

5. R/W = VIH, CE = VIL, and OE = VIL, and the address is valid prior to other coincidental with CE transition LOW.

7

APRIL 05, 2006

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