IDT723611L20PF View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT723611L20PF

CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT723611 CMOS SyncFIFO™

64 x 36

CLKB

tCLKH

tCLK

tCLKL

EF (HIGH)

CSB

W/RB

MBB

ENB

B0 - B35

PGB,

ODD/

EVEN

tENS2

tENH2

tMDV

tEN

tA

Previous Data

tPGS

tPGH

tENS2

tENH2

Word 1

tPGS

tA

tPGH

Figure 3. FIFO Read Cycle Timing

COMMERCIAL TEMPERATURE RANGES

tENS2

tENH2

No

tDIS

Operation

Word 2

3024 drw 06

CLKA

CSA

LOW

tCLK

tCLKH tCLKL

WRA

MBA

ENA

HIGH tENS3

tENS2

tENH3

tENH2

FFA HIGH tDS

tDH

A0 - A35

CLKB

EF

W1

tSKEW1(1)

tCLK

tCLKH tCLKL

1

Empty FIFO

2

tREF

tREF

CSB LOW

W/RB LOW

MBB LOW

tENS2

tENH2

ENB

B0 -B35

tA

W1

Note:

3024 drw 07

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.

Figure 4. EF Flag Timing and First Data Read when the FIFO is Empty

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