IDT72V821L20TF View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT72V821L20TF

3.3 VOLT DUAL CMOS SyncFIFO™

Integrated Device Technology 

IDT72V801/72V811/72V821/72V831/72V841/72V851

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

OPERATING CON.IGURATIONS

be grounded (see Figure 14). In this configuration, the Write Enable 2/Load

SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single WENA2/LDA(WENB2/LDB) pin is set LOW at Reset so that the pin operates

Device Configuration, the Read Enable 2 RENA2(RENB2) control input can as a control to load and read the programmable flag offsets.

WCLKA (WCLKB)

WENA1 (WENB1)

WENA2/LDA (WENB2/LDB)

DA0 - DA8 (DB0 - DB8)

FFA (FFB)

PAFA (PAFB)

RSA (RSB)

IDT

72V801

72V811

72V821

72V831

72V841

72V851

FIFO

A (B)

RCLKA (RCLKB)

RENA1 (RENB1)

OEA (OEB)

QA0 - QA8 (QB0 - QB8)

EFA (EFB)

PAEA (PAEB)

RENA2 (RENB2)

4093 drw 16

Figure 14. Block Diagram of One of the IDT72V801/72V811/72V821/72V831/72V841/72V851's

two FIFOs configured as a single device

WIDTH EXPANSION CONFIGURATION — Word width may be in-

creased simply by connecting the corresponding input control signals of

FIFOs A and B. A composite flag should be created for each of the end-

pointstatusflagsEFAandEFB,alsoFFAandFFB). ThepartialstatusflagsPAEA,

PAFB, PAEA and PAFB can be detected from any one device. Figure 15

demonstrates an 18-bit word width using the two FIFOs contained in one

IDT72V801/72V811/72V821/72V831/72V841/72V851. Any word width can

be attained by adding additional IDT72V801/72V811/72V821/72V831/

72V841/72V851s.

When these devices are in a Width Expansion Configuration, the Read

Enable 2 (RENA2 and RENB2) control inputs can be grounded (see Figure

15). In this configuration, the Write Enable 2/Load (WENA2/LDA, WENB2/LDB)

pins are set LOW at Reset so that the pin operates as a control to load and read

the programmable flag offsets.

9

RESET

RSA DB0 - DB8

RSB

DATA IN

18

9 DA0 - DA8

RAM

EFA

RAM

EFB

EMPTY FLAG

ARRAY RCLKA

ARRAY RCLKB

READ CLOCK

WRITE CLOCK

WCLKA

A

WCLKB B

WRITE ENABLE

WRITE ENABLE/LOAD

FULL FLAG

256x9 RENA1

256x9 RENB1

READ ENABLE

WENA1

512x9

WENB1 512x9

1,024x9 OEA1

1,024x9 OEB

OUTPUT ENABLE

WENA2/LDA 2,048x9 2WENB2/LDB 2,048x9

4,096x9

4,096x9

FFA

8,192x9

8,192x9 QB0 - QB8

9

18 DATA OUT

FFB

RENA2

QA0 - QA8 RENB2

9

4093 drw 17

Figure 15. Block diagram of the two FIFOs contained in one IDT72V801/72V811/72V821/72V831/72V841/72V851

configured for an 18-bit width-expansion

14

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