IDT72V3651 Datasheet PDF - Integrated Device Technology

IDT72V3651 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT72V3651

3.3 VOLT CMOS SyncFIFO™ 512 x 36 1,024 x 36 2,048 x 36

Integrated Device Technology

IDT72V3651 Datasheet PDF : 21 Pages

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IDT72V3631/72V3641/72V3651

3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36

SYNCHRONIZED FIFO FLAGS

Each IDT72V3631/72V3641/72V3651 FIFO flag is synchronized to its port

Clock through at least two flip-flop stages. This is done to improve the flags’

reliability by reducing the probability of metastable events on their outputs when

CLKA and CLKB operate asynchronously to one another. OR and AE are

synchronized to CLKB. IR and AF are synchronized to CLKA. Table 4 shows

the relationship of each flag to the number of words stored in memory.

OUTPUT READY FLAG (OR)

The Output Ready flag of a FIFO is synchronized to the port Clock that reads

data from its array (CLKB). When the OR flag is HIGH, new data is present

in the FIFO output register. When the OR flag is LOW, the previous data word

is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its

output register. The state machine that controls an OR flag monitors a write-

pointer and read-pointer comparator that indicates when the FIFO memory

status is empty, empty+1, or empty+2. From the time a word is written to a FIFO,

it can be shifted to the FIFO output register in a minimum of three cycles of CLKB.

Therefore, an OR flag is LOW if a word in memory is the next data to be sent

to the FIFO output register and three CLKB cycles have not elapsed since the

time the word was written. The OR flag of the FIFO remains LOW until the third

LOW-to-HIGH transition of CLKB occurs, simultaneously forcing the OR flag

HIGH and shifting the word to the FIFO output register.

A LOW-to-HIGH transition on CLKB begins the first synchronization cycle of

a write if the clock transition occurs at time tSKEW1 or greater after the write.

Otherwise, the subsequent CLKB cycle may be the first synchronization cycle

(see Figure 7).

COMMERCIAL TEMPERATURE RANGE

INPUT READY FLAG (IR)

The Input Ready flag of a FIFO is synchronized to the port Clock that writes

data to its array (CLKA). When the IR flag is HIGH, a memory location is free

in the FIFO to write new data. No memory locations are free when the IR flag

is LOW and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. The

state machine that controls an IR flag monitors a write-pointer and read pointer

comparator that indicates when the FIFO memory status is full, full-1, or full-2.

From the time a word is read from a FIFO, its previous memory location is ready

to be written in a minimum of three cycles of CLKA. Therefore, an IR flag is LOW

if less than two cycles of CLKA have elapsed since the next memory write location

has been read. The second LOW-to-HIGH transition on CLKA after the read

sets the Input Ready flag HIGH, and data can be written in the following cycle.

A LOW-to-HIGH transition on CLKA begins the first synchronization cycle of

a read if the clock transition occurs at time tSKEW1 or greater after the read.

Otherwise, the subsequent CLKA cycle may be the first synchronization cycle

(see Figure 8).

ALMOST-EMPTY FLAG (AE)

The Almost-Empty flag of a FIFO is synchronized to the port Clock that reads

data from its array (CLKB). The state machine that controls an AE flag monitors

a write-pointer and read-pointer comparator that indicates when the FIFO

memory status is almost-empty, almost-empty+1, or almost-empty+2. The

almost-empty state is defined by the contents of register X. This register is loaded

with a preset value during a FIFO reset, programmed from port A, or

programmed serially (see Almost-Empty flag and Almost-Full flag offset pro-

TABLE 2 — PORT-A ENABLE FUNCTION TABLE

CSA

W/RA

ENA

MBA

CLKA

Data A (A0-A35) I/O

Input

↑

Input

↑

Input

Output

↑

Output

↑

Output

Port Functions

None

FIFO Write

Mail1 Write

None

Mail2 Read (Set MBF2 HIGH)

TABLE 3 — PORT-B ENABLE FUNCTION TABLE

CSB

W/RB

ENB

MBB

CLKB

Data B (B0-A35) I/O

Input

↑

Input

↑

Input

Output

↑

Output

↑

Output

Port Functions

None

Mail2 Write

None

FIFO read

None

Mail1 Read (Set MBF1 HIGH)

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