ISL22329 View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

ISL22329

Dual Digitally Controlled Potentiometers (XDCP™)

Intersil 

ISL22329

The WIP bit (ACR[5]) is read only bit. It indicates that

non-volatile write operation is in progress. It is impossible to

write to the IVRi, WRi or ACR while WIP bit is 1.

Shutdown Mode

The device can be put in Shutdown mode either by pulling the

SHDN pin to GND or setting the SHDN bit in the ACR register

to 0. The truth table for Shutdown mode is in Table 3.

TABLE 3.

SHDN pin

SHDN bit

Mode

High

1

Normal operation

Low

1

Shutdown

High

0

Shutdown

Low

0

Shutdown

I2C Serial Interface

The ISL22329 supports an I2C bidirectional bus oriented

protocol. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master and

the device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the ISL22329

operates as a slave device in all applications.

All communication over the I2C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line must change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 12). On power-up of the ISL22329 the SDA pin is in

the input mode.

All I2C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL22329 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met

(see Figure 12). A START condition is ignored during the

power-up of the device.

All I2C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (see Figure 12). A STOP condition at the end

of a read operation, or at the end of a write operation places

the device in its standby mode.

An ACK, Acknowledge, is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (see Figure 13).

The ISL22329 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL22329 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation.

A valid Identification Byte contains 1010b as the four MSBs,

and the following three bits matching the logic values

present at pins A2, A1, and A0. The LSB is the Read/Write

bit. Its value is “1” for a Read operation, and “0” for a Write

operation (see Table 4).

TABLE 4. IDENTIFICATION BYTE FORMAT

Logic values at pins A2, A1, and A0 respectively

1

0

1

0

A2 A1 A0 R/W

(MSB)

(LSB)

SCL

SDA

START

DATA

DATA

DATA

STABLE CHANGE STABLE

STOP

FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS

10

FN6330.2

September 4, 2009

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