Philips Semiconductors
Power amplifier controller for GSM and
PCN systems
Preliminary specification
PCF5077T
FEATURES
• CMOS low-voltage, low-power
• Can be used in burst mode with power-down
• 3-wire serial bus interface with the bus available in
Power-down mode
• On-chip ramp generator for 256 different power levels
with two dynamic ranges
• Two programmable regulator start conditions (VKICK
and VHOME)
• Programmable analog output voltage limitation
• Ramping speed depending on the 13 MHz system
frequency clock for Global System for Mobile
communications (GSM) and Personal Communications
Network (PCN)
• Low swing input buffer for the 13 MHz master clock
• Compatible to a large number of different RF power
modules
• Programmable temperature matching
• Dual supply concept for analog and digital part
• No external filter for suppression of clock pulse feed
through
• Direct power control with ramping function (control loop
can be switched off)
• On-chip Power-on reset for all registers
• Serial bus is compatible to bus systems independent of
additional clock pulse after rising edge of strobe signal
• Low operating current consumption
• TTL compatible interface
• Programmable gain factor for sensor signal at OP1
• Two different voltages for 1 LSB of the burst power
Digital-to-Analog Converter (DAC) are programmable.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS MIN. TYP. MAX. UNIT
VDDD
VDDA1
VDDA2
IDD(oper)(tot)
Tamb
digital supply voltage
analog supply voltage 1
analog supply voltage 2 (for OP4)
total operating current on the VDD pins
operating ambient temperature
note 1
note 1
note 2
2.7 3.0
2.7 3.0
2.7 5.0
−
9
−40 −
6.0 V
6.0 V
6.0 V
18
mA
+85 °C
Notes
1. The voltages VDDA1 and VDDD must be equal and VDDA2 must be either equal or greater than VDDA1 = VDDD.
2. VDDA1 = VDDD = 3 V and VDDA2 = 5 V. The VDD pins are: VDDA1, VDDA2 and VDDD.
ORDERING INFORMATION
TYPE
NUMBER
PCF5077T
NAME
SSOP16
PACKAGE
DESCRIPTION
plastic shrink small outline package; 16 leads; body width 4.4 mm
VERSION
SOT369-1
1997 Nov 19
2