ISL90842(2005) View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
ISL90842 Datasheet PDF : 12 Pages
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ISL90842
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 1)
tHD:STO STOP condition hold time for From SDA rising edge to SCL falling edge. Both crossing
read, or volatile only write 70% of VCC.
tDH Output data hold time
(Note 15)
From SCL falling edge crossing 30% of VCC, until SDA
enters the 30% to 70% of VCC window.
tR
SDA and SCL rise time
(Note 15)
From 30% to 70% of VCC
600
0
20 +
0.1 * Cb
tF
SDA and SCL fall time
(Note 15)
From 70% to 30% of VCC
20 +
0.1 * Cb
Cb Capacitive loading of SDA or Total on-chip and off-chip
10
(Note 15) SCL
Rpu SDA and SCL bus pull-up Maximum is determined by tR and tF.
1
(Note 15) resistor off-chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
tSU:A A1 and A0 setup time
Before START condition
600
tHD:A A1 and A0 hold time
After STOP condition
600
MAX
250
250
400
UNITS
ns
ns
ns
ns
pF
kΩ
ns
ns
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
A0 and A1 Pin Timing
SCL
START
SDA IN
A0, A1
tSU:A
CLK 1
STOP
tHD:A
5
FN8096.0
June 14, 2005
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