ISP1181A View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
ISP1181A Datasheet PDF : 70 Pages
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Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Table 7: Endpoint selection for DMA transfer…continued
Endpoint
identifier
EPIDX[3:0]
Transfer direction
EPDIR = 0
EPDIR = 1
12
1101
OUT: read
IN: write
13
1110
OUT: read
IN: write
14
1111
OUT: read
IN: write
10.2 8237 compatible mode
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware
Configuration Register (see Table 20). The pin functions for this mode are shown in
Table 8.
Table 8:
Symbol
DREQ
DACK
EOT
RD
WR
8237 compatible mode: pin functions
Description
I/O
Function
DMA request
O
ISP1181A requests a DMA transfer
DMA acknowledge
I
DMA controller confirms the transfer
end of transfer
I
DMA controller terminates the transfer
read strobe
I
instructs ISP1181A to put data on the bus
write strobe
I
instructs ISP1181A to get data from the
bus
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of ISP1181A in 8237 compatible DMA mode is given in Figure 4.
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and
HLDA (Hold Acknowledge). The bus operation is controlled via MEMR (Memory
Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
AD0,
DATA1 to DATA15
ISP1181A
DREQ
DACK
RD
WR
RAM
MEMR
MEMW
DMA
CONTROLLER
8237
DREQ
HRQ
DACK
HLDA
IOR
IOW
Fig 4. ISP1181A in 8237 compatible DMA mode.
CPU
HRQ
HLDA
004aaa022
9397 750 13959
Product data
Rev. 05 — 08 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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