Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
9. Interrupts
A hardware reset disables all USB endpoints and clears all Endpoint Configuration
registers (ECRs), except for the control endpoint that is fixed and always enabled.
Section 10.3 explains how to (re)initialize endpoints.
Figure 8 shows the interrupt logic of the ISP1183. Each of the indicated USB events
is logged in a status bit of the Interrupt register. Corresponding bits in the Interrupt
Enable register determine whether an event will generate an interrupt.
Interrupts can be masked globally using bit INTENA of the Mode register (see
Table 18).
The signaling mode of output INT is controlled by bit INTLVL of the Hardware
Configuration register (see Table 20). Default settings after reset is level mode. When
pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination
of all interrupt bits changes from logic 0 to logic 1.
reset interrupt source
IERST
suspend interrupt source
IESUSP
IERESM
IESOF
IEP14
...
IEP0IN
IEP0OUT
.
.
.
.
.
.
.
.
.
.
.
.
EPn interrupt source
Fig 8. Interrupt logic.
(clear EPn interrupt; reading EPn
status register will set this signal)
(clear SUSPEND interrupt; reading
interrupt register will set this signal)
(clear RESET interrupt; reading
interrupt register will set this signal)
RESET
SUSPND
.
RESUME
.
.
.
SOF
.
.
.
.
EP14
.
.
...
.
.
EP0IN
EP0OUT
interrupt register
RESET
INTENA
device mode
register
PULSE
GENERATOR
INTLVL
hardware configuration
register
1
INT
0
004aaa255
9397 750 11804
Product data
Bits SUSPND, RESET, RESUME, SP_EOT, EOT and SOF are cleared when the
Interrupt register is read. The endpoint bits (EP0OUT to EP14) are cleared when the
associated Endpoint Status register is read.
Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the
current bus status when reading the Interrupt register.
Rev. 01 — 24 February 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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