LH28F004SU-Z9 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F004SU-Z9

4M (512 × 8) Flash Memory

Sharp Electronics 

4M (512K × 8) Flash Memory

LH28F004SU-Z9

PIN DESCRIPTIONS

SYMBOL

TYPE

NAME AND FUNCTION

A0 - A13 INPUT

WORD-SELECT ADDRESSES: Select a word within one 16K block. These addresses

are latched during Data Writes.

A14 - A18 INPUT

BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are

latched during Data Writes, Erase and Lock-Block operations.

DATA INPUT/OUTPUT: Inputs data and commands during CUI write cycles. Outputs

DQ0 - DQ7 INPUT/OUTPUT array, buffer, identifier or status data in the appropriate Read mode. Floated when the

chip is de-selected or the outputs are disabled.

CE » INPUT

CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and

sense amplifiers. CE» must be low to select the device.

RP » INPUT

RESET/POWER-DOWN: With RP » low, the device is reset, any current operation is

aborted and device is put into the deep power down mode. When the power is turned

on, RP » pin is turned to low in order to return the device to default configuration. When

the power transition has occurred, or the power on/ off ,RP» is required to stay low in

order to protect data from noise. When returning from Deep Power-Down, a recovery

time of 750 ns is required to allow these circuits to power-up. When RP» goes low, any

current or pending WSM operation(s) are terminated, and the device is reset. All

Status registers return to ready (with all status flags cleared). After returning, the

device is in read array mode.

OE» INPUT

OUTPUT ENABLE: Gates device data through the output buffers when low. The

outputs float to tri-state off when OE» is high.

WE INPUT

WRITE ENABLE: Controls access to the CUI, Data Queue Registers and Address Queue

Latches. WE is active low, and latches both address and data (command or array) on

its rising edge.

RY »/BY »

OPEN DRAIN

OUTPUT

READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM

is busy performing an operation. When the WSM is ready for new operation or Erase is

Suspended, or the device is in deep power-down mode RY»/BY » pin is floated.

VPP

SUPPLY

ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V): For erasing memory array blocks or

writing words/bytes into the flash array.

VCC

SUPPLY

DEVICE POWER SUPPLY (READ 2.7 V ~ 3.6 V,WRITE/ERASE 2.7 V ~ 3.3 V): Do not

leave any power pins floating.

GND SUPPLY

GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.

NC

NO CONNECT: No internal connection to die, lead may be driven or left floating

DESCRIPTION

The LH28F004SU is a high performance 4M

(4,194,304 bit) block erasable non-volatile random ac-

cess memory organized as 512K × 8.The LH28F004SU

includes thirty-two 16K (16,384) blocks. A chip memory

map is shown in Figure 3.

The implementation of a new architecture, with many

enhanced features, will improve the device operating

characteristics and results in greater product reliability

and ease of use.

Among the significant enhancements of the

LH28F004SU:

• 3 V Read, 5 V Write/Erase Operation

(5 V VPP, 2.7 V VCC)

• Low Power Capability

(2.7 V VCC Read and Write/Erase)

• Improved Write Performance

• Dedicated Block Write/Erase Protection

• Command-Controlled Memory Protection

Set/Reset Capability

3

Share Link: