LM3S608-IQC20-B0 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

LM3S608-IQC20-B0

LM3S608 Microcontroller

Unspecified 

LM3S608 Microcontroller

– Programmable interrupt generation logic with interrupt masking

– Lock register protection from runaway software

– Reset generation logic with an enable/disable

– User-enabled stalling when the controller asserts the CPU Halt flag during debug

■ Synchronous Serial Interface (SSI)

– Master or slave operation

– Programmable clock bit rate and prescale

– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments

synchronous serial interfaces

– Programmable data frame size from 4 to 16 bits

– Internal loopback test mode for diagnostic/debug testing

■ UART

– Two fully programmable 16C550-type UARTs

– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service

loading

– Programmable baud-rate generator with fractional divider

– Programmable FIFO length, including 1-byte deep operation providing conventional

double-buffered interface

– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

– Standard asynchronous communication bits for start, stop, and parity

– False-start-bit detection

– Line-break generation and detection

■ ADC

– Single- and differential-input configurations

– Eight 10-bit channels (inputs) when used as single-ended inputs

– Sample rate of 500 thousand samples/second

– Flexible, configurable analog-to-digital conversion

– Four programmable sample conversion sequences from one to eight entries long, with

corresponding conversion result FIFOs

– Each sequence triggered by software or internal event (timers, analog comparators, or GPIO)

October 01, 2007

21

Preliminary

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