LM3S801 View Datasheet(PDF) - Unspecified
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LM3S801 Datasheet PDF : 397 Pages
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LM3S801 Data Sheet
Register 5:
Register 6:
Register 7:
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Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 256
SSI Interrupt Mask (SSIIM), offset 0x014 ................................................................................ 257
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .................................................................... 258
SSI Masked Interrupt Status (SSIMIS), offset 0x01C.............................................................. 259
SSI Interrupt Clear (SSIICR), offset 0x020.............................................................................. 260
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0.................................................. 261
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4.................................................. 262
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8.................................................. 263
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ................................................. 264
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0.................................................. 265
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4.................................................. 266
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8.................................................. 267
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ................................................. 268
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0..................................................... 269
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4..................................................... 270
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8..................................................... 271
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .................................................... 272
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 273
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ................................................................ 284
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004................................................................. 285
Register 3: I2C Master Data (I2CMDR), offset 0x008................................................................................ 290
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ................................................................ 291
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ............................................................... 292
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ...................................................... 293
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ................................................ 294
I2C Master Interrupt Clear (I2CMICR), offset 0x01C ............................................................... 295
I2C Master Configuration (I2CMCR), offset 0x020 .................................................................. 296
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 .................................................................. 297
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ................................................................. 298
Register 12: I2C Slave Data (I2CSDR), offset 0x008................................................................................... 300
Register 13:
Register 14:
Register 15:
Register 16:
I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ................................................................. 301
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010......................................................... 302
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014................................................... 303
I2C Slave Interrupt Clear (I2CSICR), offset 0x018 .................................................................. 304
Analog Comparators .................................................................................................................... 305
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00........................................ 310
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04.............................................. 311
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ................................................ 312
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ............................ 313
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ............................................................ 314
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ............................................................ 314
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ............................................................ 314
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ............................................................. 315
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ............................................................. 315
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ............................................................. 315
Pulse Width Modulator (PWM)..................................................................................................... 317
Register 1: PWM Master Control (PWMCTL), offset 0x000....................................................................... 325
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004................................................................. 326
October 8, 2006
15
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