LPC2102 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC2102

Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC

NXP Semiconductors. 

NXP Semiconductors

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers

Table 3. Pin description …continued

Symbol

Pin

Type

P0.22/AD0.0 32[3]

I/O

I

P0.23/AD0.1 33[3]

I/O

I

P0.24/AD0.2 34[3]

I/O

I

P0.25/AD0.6 38[3]

I/O

I

P0.26/AD0.7 39[3]

I/O

I

P0.27/TRST/ 8[1]

I/O

CAP2.0

I

I

P0.28/TMS/

9[1]

I/O

CAP2.1

I

I

P0.29/TCK/

10[1]

I/O

CAP2.2

I

I

P0.30/TDI/

15[1]

I/O

MAT3.3

I

O

P0.31/TDO

16[1]

O

O

RTCX1

20[6]

I

RTCX2

25[6]

O

RTCK

26[6]

I/O

XTAL1

11

I

XTAL2

12

O

DBGSEL

27

I

RST

6

I

VSS

VSSA

VDDA

7, 19, 43

I

31

I

42

I

LPC2101_02_03_3

Product data sheet

Description

P0.22 — General purpose input/output digital pin.

AD0.0 — ADC 0, input 0.

P0.23 — General purpose input/output digital pin.

AD0.1 — ADC 0, input 1.

P0.24 — General purpose input/output digital pin.

AD0.2 — ADC 0, input 2.

P0.25 — General purpose input/output digital pin.

AD0.6 — ADC 0, input 6.

P0.26 — General purpose input/output digital pin.

AD0.7 — ADC 0, input 7.

P0.27 — General purpose input/output digital pin.

TRST — Test Reset for JTAG interface.

CAP2.0 — Capture input for Timer 2, channel 0.

P0.28 — General purpose input/output digital pin.

TMS — Test Mode Select for JTAG interface.

CAP2.1 — Capture input for Timer 2, channel 1.

P0.29 — General purpose input/output digital pin.

TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of

the CPU clock (CCLK) for the JTAG interface to operate.

CAP2.2 — Capture input for Timer 2, channel 2.

P0.30 — General purpose input/output digital pin.

TDI — Test Data In for JTAG interface.

MAT3.3 — PWM output 3 for Timer 3.

P0.31 — General purpose output only digital pin.

TDO — Test Data Out for JTAG interface.

Input to the RTC oscillator circuit.

Output from the RTC oscillator circuit.

Returned test clock output: Extra signal added to the JTAG port. Assists

debugger synchronization when processor frequency varies. Bidirectional pin

with internal pull-up.

Input to the oscillator circuit and internal clock generator circuits.

Output from the oscillator amplifier.

Debug select: When LOW, the part operates normally. When HIGH, debug

mode is entered. Input with internal pull-down.

External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

Ground: 0 V reference.

Analog ground: 0 V reference. This should be nominally the same voltage

as VSS but should be isolated to minimize noise and error.

Analog 3.3 V power supply: This should be nominally the same voltage as

VDD(3V3) but should be isolated to minimize noise and error. The level on this

pin also provides a voltage reference level for the ADC.

Rev. 03 — 7 October 2008

© NXP B.V. 2008. All rights reserved.

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