LTC1605-2IG View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC1605-2IG

Single Supply 16-Bit, 100ksps, Sampling ADCs

Linear Technology 

TEST CIRCUITS

Load Circuit for Access Timing

5V

DBN

1k

1k

DBN

CL

CL

A. HI-Z TO VOH AND VOL TO VOH

1605-1/2 TC01

B. HI-Z TO VOL AND VOH TO VOL

LTC1605-1/LTC1605-2

Load Circuit for Output Float Delay

5V

DBN

1k

50pF

A. VOH TO HI-Z

1k

DBN

50pF

1605-1/2 TC02

B. VOL TO HI-Z

APPLICATIONS INFORMATION

Conversion Details

The LTC1605-1/LTC1605-2 use a successive approxi-

mation algorithm and an internal sample-and-hold cir-

cuit to convert an analog signal to a 16-bit or two byte

parallel output. The ADC is complete with a precision

reference and an internal clock. The control logic pro-

vides easy interface to microprocessors and DSPs. (Please

refer to the Digital Interface section for the data format.)

Conversion start is controlled by the CS and R/C inputs.

At the start of conversion, the successive approximation

register (SAR) is reset. Once a conversion cycle has

begun, it cannot be restarted.

During the conversion, the internal 16-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

Figure 1, VIN is connected through the resistor divider

and S1 to the sample-and-hold capacitor during the

acquire phase and the comparator offset is nulled by the

RIN1

VIN

RIN2

S1

SAMPLE

CSAMPLE

HOLD

S2

CDAC

DAC

VDAC

SAMPLE

S3

–

+

COMPARATOR

S

A

R

16-BIT

LATCH

1605-1/2 F01

Figure 1. LTC1605-1/LTC1605-2 Simplified Equivalent Circuit

autozero switch, S3. In this acquire phase, a minimum

delay of 2µs will provide enough time for the sample-and-

hold capacitor to acquire the analog signal. During the

convert phase, S3 opens, putting the comparator into the

compare mode. The input switch S2 switches CSAMPLE to

ground, injecting the analog input charge onto the sum-

ming junction. This input charge is successively com-

pared with the binary-weighted charges supplied by the

capacitive DAC. Bit decisions are made by the high speed

comparator. At the end of a conversion, the DAC output

balances the VIN input charge. The SAR contents (a 16-

bit data word) that represents the VIN are loaded into the

16-bit output latches.

Driving the Analog Inputs

The nominal input range for the LTC1605-1 is 0V to 4V or

(1.6VREF) and for the LTC1605-2 the input range is ±4V

or (±1.6VREF). The inputs are overvoltage protected to

±25V. The input impedance is typically 10kΩ; therefore,

it should be driven by a low impedance source. Wideband

noise coupling into the input can be minimized by placing

a 1000pF capacitor at the input as shown in Figure 2. An

NPO-type capacitor gives the lowest distortion. Place the

capacitor as close to the device input pin as possible. If

an amplifier is to be used to drive the input, care should

be taken to select an amplifier with adequate accuracy,

linearity and noise for the application. The following list

is a summary of the op amps that are suitable for driving

the LTC1605-1/LTC1605-2. More detailed information is

available in the Linear Technology data books and

LinearViewTM CD-ROM.

LinearView is a trademark of Linear Technology Corporation

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