LH543611 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH543611

512 × 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO

Sharp Electronics 

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

RESOURCE-

REGISTER

ADDRESS

A2A A1A A0A

D35A

H H H X...

Table 3b. LH543621 Resource-Register Programming

RESOURCE-REGISTER CONTENTS

NORMAL FIFO OPERATION

LH543611/21

D0A

...X

D35A

H H L X...

HLH

D35A . . . D27A

AF2 Offset 1

MAILBOX

D0A

...X

AF2, AE2, AF1, AE1 FLAG REGISTER (36-BIT MODE)4

D26A . . . D18A

AE2 Offset 1

D17A . . . D9A

AF1 Offset 1

D8A . . . D0A

AE1 Offset 1

D35A

H L L X...

CONTROL REGISTER: FLAG SYNCHRONIZATION, PARITY CONFIGURATION

D18A D17A

D9A

...X Port B Control 3

D8A

D1A D0A

Port A Control 3 PM 2

D35A

L H H X...

10-BIT AE1 FLAG OFFSET REGISTER

D10A

...X

D9A . . . D0A

AE1 Offset 1

D35A

L H L X...

10-BIT AF1 FLAG OFFSET REGISTER

D10A

...X

D9A . . . D0A

AF1 Offset 1

D35A

L L H X...

10-BIT AE2 FLAG OFFSET REGISTER

D10A

...X

D9A . . . D0A

AE2 Offset 1

LL

NOTES:

D35A

L X...

10-BIT AF2 FLAG OFFSET REGISTER

D10A

...X

D9A . . . D0A

AF2 Offset 1

1. All four programmable-flag-offset values are initialized to eight (8) during a reset operation.

2. Parity Mode: Odd parity = HIGH; even parity = LOW. The parity mode is initialized to odd during a reset operation.

3. See Tables 5 and 6 and Figure 10 for the detailed format of the Control Register word.

4. For 36-bit Flag Register Control word, with only only 9 bits to program per flag offset:

Offset is limited to a value of 511. If a greater value is desired, individual flag offset register programming is required.

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