M5M4V4265CJ-5 View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
Manufacturer
M5M4V4265CJ-5 Datasheet PDF : 31 Pages
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MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted)
Symbol
CI (A)
CI (CLK)
CI / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
VI=VSS
f=1MHz
VI=25mVrms
Limits
Min Typ Max
Unit
5
pF
7
pF
7
pF
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Symbol
Parameter
tCAC
tRAC
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
Limits
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
Min Max Min Max Min Max
(Note 7,8)
13
15
20
ns
(Note 7,9)
50
60
70
ns
(Note 7,10)
25
30
35
ns
(Note 7,11)
28
33
38
ns
(Note 7)
13
15
20
ns
(Note 13)
5
5
5
ns
(Note 13)
5
5
5
ns
(Note 7)
5
5
5
ns
(Note 12)
13
15
20
ns
(Note 12)
13
15
20
ns
(Note 12,13)
13
15
20
ns
(Note 12,13)
13
15
20
ns
Note 6 : An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7 : Measured with a load circuit equivalent to 50pF, VOH (IOH=-2mA) and VOL(IOL=2mA). The reference levels for measuring of output signals are
2.0V(VOH) and 0.8V(VOL).
8 : Assumes that tRCD≥tRCD(max) and tASC≥tASC(max) and tCP≥tCP(max).
9 : Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC
will increase by amount that tRCD exceeds the value shown.
10 : Assumes that tRAD≥tRAD(max) and tASC≤tASC(max).
11 : Assumes that tCP≤tCP(max) and tASC≥tASC(max).
12 : tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT≤ ±5µA ) and is not
reference to VOH(min) or VOL(max).
13 : Output is disabled after both RAS and CAS go to high.
4 M5M4V4265CJ,TP-5,-5S:under development
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