M62463AFP View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

M62463AFP

Dolby Pro Logic Surround Decoder

Renesas Electronics 

M62463AFP

Serial Data Control Format

(1) Data input format

DATA is read at the rising edge of SCK, and loaded last 16 bits at the rising edge of REQ.

DATA

SCK

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 "H"

REQ

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

L

L

Mode set Pro

Center

Logic

mode

Sch volume

L

H

mode

H

Delay time

Auto- set to

balance "L"

Cch volume

Chip

address

H

L

Noise sequencer

Surround/echo mode

H

Test mode (user inhibit)

(2) Control condition

No.

Control Mode

1 Mode set

2 Pro Logic mode

3 Center mode

4 Delay time

5 Auto-balance

6 Noise sequencer

7 Surround/echo mode

8 Cch/Sch volume

9 Chip address

Contents

Normal stereo/Dolby Pro Logic/space surround or echo/mute

4 ch Pro Logic/3 ch stereo

Wide/Normal/Phantom/OFF

15.4, 20.5, 25.6, 29.2, 51.2 ms (for surround)

123,184 ms (for echo)

Input auto-balance ON/OFF

ON/OFF Lch/Rch/Cch/Sch

Delay input L – R/(L + R) / 2 /MICin

Feedback volume, microphone volume, delay output mixing

0 to –87 dB / 1 dB step, and –∞

Input data effect or not

(3) Set conditions

Mode Setting (D0 = "L", D1 = "L")

D2

D3

L

L

L

H

H

L

H

H

Condition

Normal stereo (bypass)

Dolby Pro Logic surround

Space surround/echo

Output mute

Pro Logic Mode Setting (D0 = "L", D1 = "L")

D4

Condition

L

4 ch Pro Logic

H

3 ch stereo

Center Mode Setting (D0 = "L", D1 = "L")

D5

D6

Condition

L

L

Wide

L

H

Normal

H

L

Phantom

H

H

OFF

REJ03F0275-0200 Rev.2.00 Jun 16, 2008

Page 8 of 16

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