Dual 180° Out-of-Phase PWM Step-
Down Controllers with POR
VIN
6V - 23V
RV+
4.7Ω
0.1µF
OUTPUT1
VOUT = 1.8V
COUT1
4 × 220µF
CIN1
2 × 10µF
L1
1µH
CV+
0.22µF
NH1*
R1A
8.06kΩ
**
NL1*
V+
4.7Ω
CBST1
0.1µF
BST1
DH1
LX1
DL1
PGND
VL
4.7Ω
BST2
CBST2
0.1µF
DH2
LX2
DL2
CVL
4.7µF
CIN2
2 × 10µF
NH2*
L2
1.2µH
NL2*
**
R2A
15kΩ
R1B
10kΩ
CCOMP1A
10nF
RCOMP1
5.9kΩ
CCOMP1B
100pF
D2
CMSSH-3
CLOCK OUTPUT
RESET OUTPUT
ON
OFF
FB1
COMP1
FB2
COMP2
MAX1875
MAX1876 REF
OSC
GND
CKO
SYNC
RST (MAX 1876 ONLY)
ILIM1
EN
ILIM2
84.5kΩ
RCOMP2
8.2kΩ
CCOMP2B
100pF
CREF
0.22µF
D3
CMSSH-3
CCOMP2A
6.8nF
R2B
10kΩ
VL
96.5kΩ
140kΩ
118kΩ
*IRF7811W
**OPTIONAL
OUTPUT2
VOUT = 2.5V
COUT2
4 × 220µF
Figure 1. Standard Application Circuit
With dual synchronized out-of-phase operation, the
MAX1875/MAX1876’s high-side MOSFETs turn-on 180°
out-of-phase. The instantaneous input current peaks of
both regulators no longer overlap, resulting in reduced
RMS ripple current and input voltage ripple. This reduces
the required input capacitor ripple-current rating, allow-
ing fewer or less expensive capacitors, and reduces
shielding requirements for EMI. The Out-of-Phase
Waveforms in the Typical Operating Characteristics
demonstrate synchronized 180° out-of-phase operation.
Internal 5V Linear Regulator (VL)
All MAX1875/MAX1876 functions are internally powered
from an on-chip, low-dropout 5V regulator. The maxi-
mum regulator input voltage (V+) is 23V. Bypass the
regulator’s output (VL) with a 4.7µF ceramic capacitor
to PGND. The VL dropout voltage is typically 500mV, so
when V+ is greater than 5.5V, VL is typically 5V. The
MAX1875/MAX1876 also employs an undervoltage
lockout circuit that disables both regulators when VL
falls below 4.5V. VL should also be bypassed to GND
with a 0.1µF capacitor.
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