MB91625 Series
• A/D converter
• 16 channels, 1 unit
• 10-bit resolution
• Conversion time : approx. 1.2 μs (PCLK = 33 MHz)
• Priority conversion (2 levels)
• Conversion modes : Single-shot conversion mode, scan conversion mode
• Activation sources : Software, external trigger, base timer
• Built-in FIFO for storing conversion data (for scan conversion:16, for priority conversion:4)
• D/A converter
• 2 channels
• 8-bit resolution
• Base timer
• 16 channels
• Operation mode is selectable from the followings for each channel
- 16/32-bit reload timer
- 16-bit PWM timer
- 16/32-bit PWC timer
- 16-bit PPG timer
• Cascading connection between 2 channels allows them to be used as one 32-bit timer
• Multiple channels can be started simultaneously
• Input/output select function
• 16-bit reload timer
• 3 channels (including 1 channel for REALOS)
• Interval timer function
• Count clock select function (peripheral clock (PCLK) divided by 2 to 64)
• Compare timer
• 32-bit input capture : 8 channels
• 32-bit output compare : 8 channels
• 32-bit free-run timer : 2 channels
• Other interval timers
• Up/down counter : 4 channels
• Watch counter : 1 channel
• Watchdog timer : 1 channel
• Main timer
• 1 channel
• Counts the oscillation stabilization wait time of the main clock (MCLK)
• Counts the oscillation stabilization wait time of the PLL clock (PLLCLK)
• Can be used as an interval timer while the main clock (MCLK) oscillations is stable
• Sub timer
• 1 channel
• Counts the oscillation stabilization wait time of the sub clock (SBCLK)
• Can be used as an interval timer while the sub clock (SBCLK) oscillations is stable
(Continued)
DS07-16908-1E
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