MC100LVEL51(2016) View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

MC100LVEL51
(Rev.:2016)

3.3V ECL Differential Clock D Flip‐Flop

ON Semiconductor 

MC100LVEL51

R1

D2

CLK 3

R

D

Flip-Flop

8 VCC

7Q

6Q

CLK 4

5 VEE

Figure 1. Logic Diagram and Pinout Assignment

Table 1. PIN DESCRIPTION

Table 2. TRUTH TABLE

PIN

FUNCTION

D

R

CLK

Q

CLK, CLK

Q, Q

D

ECL Differential Clock Input

ECL Differential Output

ECL D Input

L

L

Z

L

H

L

Z

H

X

H

X

L

R

ECL Reset Input

VCC

Positive Supp;y

VEE

Negative Supply

Z = LOW to HIGH Transition

X = Don’t Care

EP

(DFN8 only) Thermal exposed pad must be

connected to a sufficient thermal conduit. Elec-

trically connect to the most negative supply

(GND) or leave unconnected, floating open.

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