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MC14536BDW View Datasheet(PDF) - Motorola => Freescale

Part Name
Description
Manufacturer
MC14536BDW
Motorola
Motorola => Freescale 
MC14536BDW Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
RX
PULSE
GEN.
CLOCK
CX
+V
16
6 8–BYPASS VDD
9A
OUT 1
4
10 B
11 C
12 D
2 RESET
OUT 2 5
1 SET
7 CLOCK INH
15 MONO–IN
14 CLOCK INH
3 IN1
VSS DECODE OUT
13
8
IN1
RESET
DECODE OUT
*tw
POWER UP
*tw .00247 RX CX0.85
tw in µsec
RX in k
CX in pF
NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
input low enables the chip’s internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes
Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock
period) intervals where n = the number of stages selected from the truth table.
Figure 10. Time Interval Configuration Using an External Clock, Reset,
and Output Monostable to Achieve a Pulse Output
(Divide–by–4 Configured)
MC14536B
10
MOTOROLA CMOS LOGIC DATA

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