MC1495 View Datasheet(PDF) - ON Semiconductor
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MC1495 Datasheet PDF : 20 Pages
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MC1495
Divide Circuit
Consider the circuit shown in Figure 24 in which the
multiplier is placed in the feedback path of an operational
amplifier. For this configuration, the operational amplifier
will maintain a “virtual ground” at the inverting (−) input.
Assuming that the bias current of the operational amplifier
is negligible, then I1 = I2 and,
KVXVY = −VZ
R1
R2
(1)
Solving for VY,
−R1
VY = R2 K
VZ
VX
(2)
If R1=R2,
VY =
−VZ
KVX
(3)
If R1= KR2,
VY =
−VZ
VX
(4)
Hence, the output voltage is the ratio of VZ to VX and
provides a divide function. This analysis is, of course, the
ideal condition. If the multiplier error is taken into account,
the output voltage is found to be:
VY = −
R1
R2 K
VZ ∆E
VX + KVX
(5)
where ∆E is the error voltage at the output of the multiplier.
From this equation, it is seen that divide accuracy is strongly
dependent upon the accuracy at which the multiplier can be
set, particularly at small values of VY. For example, assume
that R1 = R2, and K = 1/10. For these conditions the output
of the divide circuit is given by:
VY
=
−10 VZ
VX
+
10 ∆E
VX
(6)
From Equation 6, it is seen that only when VX = 10 V is
the error voltage of the divide circuit as low as the error of
the multiply circuit. For example, when VX is small, (0.1 V)
the error voltage of the divide circuit can be expected to be
a hundred times the error of the basic multiplier circuit.
In terms of percentage error,
percentage
error
=
error
actual
x
100%
or from Equation (5),
∆E
PED =
KVX
R1 VZ
=
R2
R1
∆E
VZ
(7)
R2 K VX
From Equation 7, the percentage error is inversely related
to voltage VZ (i.e., for increasing values of VZ, the
percentage error decreases).
A circuit that performs the divide function is shown in
Figure 25.
Two things should be emphasized concerning Figure 25.
1. The input voltage (VX′) must be greater than zero and
must be positive. This insures that the current out of
Pin 2 of the multiplier will always be in a direction
compatible with the polarity of VZ.
2. Pin 2 and 14 of the multiplier have been interchanged
in respect to the operational amplifiers input
terminals. In this instance, Figure 25 differs from the
circuit connection shown in Figure 21; necessitated to
insure negative feedback around the loop.
A suggested adjustment procedure for the divide circuit.
1. Set VZ = 0 V and adjust the output offset
potentiometer (P4) until the output voltage (VO)
remains at some (not necessarily zero) constant value
as VX′ is varied between +1.0 V and +10 V.
2. Keep VZ at 0 V, set VX′ at +10 V and adjust the Y input
offset potentiometer (P1) until VO = 0 V.
3. Let VX′ = VZ and adjust the X-input offset
potentiometer (P2) until the output voltage remains at
some (not necessarily − 10 V) constant value as VZ =
VX′ is varied between +1.0 and +10 V.
4. Keep VX′ = VZ and adjust the scale factor
potentiometer (P3) until the average value of VO is
−10 V as VZ = VX′ is varied between +1.0 V and
+10 V.
5. Repeat steps 1 through 4 as necessary to achieve
optimum performance.
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