MC68HC908AS32AFU View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MC68HC908AS32AFU

Microcontrollers

Freescale Semiconductor 

5.0 Volt DC Electrical Characteristics

19.5 5.0 Volt DC Electrical Characteristics

Characteristic(1)

Output high voltage

ILoad = –2.0 mA (all ports)

ILoad = –5.0 mA (all ports)

Total source current

Output low voltage

ILoad = 1.6 mA (all ports)

ILoad = 10.0 mA (all ports)

Total sink current

Input high voltage

All ports, IRQs, RESET, OSC1

Input low voltage

All ports, IRQs, RESET, OSC1

VDD supply current

Run(2)

Wait(3)

Stop(4)

LVI enabled, TA = 25°C

LVI disabled, TA = 25°C

LVI enabled, –40°C to +125°C

LVI disabled, –40°C to +125°C

I/O ports Hi-Z leakage current

Input current

Capacitance

Ports (as input or output)

Low-voltage reset inhibit

Trip

Recover

POR rearm voltage(6)

POR reset voltage(7)

POR rise time ramp rate(8)

High COP disable voltage(9)

Monitor mode entry voltage on IRQ(10)

Symbol

Min

VOH

IOH(TOT)

VDD –0.8

VDD –1.5

—

VOL

IOL(TOT)

VIH

VIL

—

—

—

0.7 x VDD

VSS

Typical

—

—

—

—

—

—

—

—

Max

—

—

10

0.4

1.5

15

VDD

0.3 x VDD

Unit

V

mA

V

mA

V

V

—

—

IDD(5)

—

—

—

—

IL

–1

IIn

–1

COut

—

CIn

—

25

35

mA

14

20

mA

100

400

µA

35

50

µA

—

500

µA

—

100

µA

—

1

µA

—

1

µA

—

12

8

pF

VLVI

3.80

—

—

V

—

—

4.49

VPOR

0

—

200

mV

VPORRST

0

—

800

mV

RPOR

0.02

—

—

V/ms

VTST

VDD + 3.0

—

VDD + 4.5

V

VTST

VDD + 3.0

—

VDD + 4.5

V

1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +TA(MAX), unless otherwise noted.

2. Run (Operating) IDD measured using external square wave clock source (fBus = 8.4 MHz). All inputs 0.2 V from rail. No dc

loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly

affects run IDD. Measured with all modules enabled. Typical values at midpoint of voltage range, 25°C only.

3. Wait IDD measured using external square wave clock source (fBus = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc loads.

Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects

wait IDD. Measured with all modules enabled. Typical values at midpoint of voltage range, 25°C only.

4. Stop IDD measured with OSC1 = VSS. Typical values at midpoint of voltage range, 25°C only.

5. Although IDD is proportional to bus frequency, a current of several mA is present even at very low frequencies.

6. Maximum is highest voltage that POR is guaranteed.

7. Maximum is highest voltage that POR is possible.

8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum

VDD is reached.

9. See 8.8 COP Module During Break Interrupts. VTST applied to RST.

10. See monitor mode description within Chapter 8 Computer Operating Properly (COP). VTST applied to IRQ or RST

MC68HC908AS32A Data Sheet, Rev. 2.0

Freescale Semiconductor

261

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