MCIMX255AJM4A(2010) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MCIMX255AJM4A
(Rev.:2010)

i.MX25 Applications Processor for Automotive Products

Freescale Semiconductor 

3.7.20.2 USB Parallel Interface Timing

Table 96 defines the USB parallel interface signals.

Table 96. Signal Definitions for USB Parallel Interface

Name

Direction

Signal Description

USB_Clk

In Interface clock—All interface signals are synchronous to USB_Clk

USB_Data[7:0]

I/O Bidirectional data bus, driven low by the link during idle—Bus ownership is determined by the

direction

USB_Dir

In Direction—Control the direction of the data bus

USB_Stp

Out Stop—The link asserts this signal for one clock cycle to stop the data stream currently on the bus

USB_Nxt

In Next—The PHY asserts this signal to throttle the data

Figure 97 shows the USB parallel mode transmit/receive waveform. Table 97 describes the timing

parameters (USB15–USB17) shown in the figure.

USB_Clk

USB_Stp

USB_Data

USB_Dir/Nxt

US15

US15

US16

US16

US17

US17

Figure 97. USB Parallel Mode Transmit/Receive Waveform

Table 97. USB Timing Specification in Parallel Mode

ID

US15

US16

US17

Parameter

Setup time (Dir&Nxt in, Data in)

Hold time (Dir&Nxt in, Data in)

Output delay time (Stp out, Data out

Min.

Max.

Unit

—

6.0

ns

—

0.0

ns

—

9.0

ns

Conditions/

Reference Signal

10 pF

10 pF

10 pF

4 Package Information and Contact Assignment

4.1 400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch

Figure 98 shows the 17×17 mm i.MX25 production package. The following notes apply to Figure 98:

• All dimensions in millimeters.

• Dimensioning and tolerancing per ASME Y14.5M-1994.

i.MX25 Applications Processor for Automotive Products, Rev. 5

124

Freescale Semiconductor

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