Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
SYSCLK
VM
VM
VM CVIL
CVIH
tKHKL
tKR
tKF
tSYSCLK
VM = Midpoint Voltage (OVDD/2)
Figure 3. SYSCLK Input Timing Diagram
5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7448 as defined in Figure 4 and
Figure 5.
Table 9. Processor Bus AC Timing Specifications1
At recommended operating conditions. See Table 4.
Parameter
All Speed Grades
Symbol 2
Unit
Notes
Min
Max
Input setup times:
ns
A[0:35], AP[0:4]
tAVKH
1.5
—
—
D[0:63], DP[0:7]
tDVKH
1.5
—
—
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:4],
tIVKH
1.5
—
—
QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL[0:1]
tMVKH
1.5
—
8
Input hold times:
A[0:35], AP[0:4]
tAXKH
0
D[0:63], DP[0:7]
tDXKH
0
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL, TT[0:4],
tIXKH
0
QACK, TA, TBEN, TEA, TS, EXT_QUAL, PMON_IN,
SHD[0:1]
BMODE[0:1], BVSEL[0:1]
tMXKH
0
ns
—
—
—
—
—
—
—
—
8
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
BR, CI, DRDY, GBL, HIT, PMON_OUT, QREQ, TBST,
TSIZ[0:2], TT[0:4], WT
TS
ARTRY, SHD[0:1]
tKHAV
—
tKHDV
—
tKHOV
—
tKHTSV
—
tKHARV
—
ns
1.8
1.8
1.8
1.8
1.8
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
BR, CI, DRDY, GBL, HIT, PMON_OUT, QREQ, TBST,
TSIZ[0:2], TT[0:4], WT
TS
ARTRY, SHD[0:1]
ns
tKHAX
0.5
—
tKHDX
0.5
—
tKHOX
0.5
—
tKHTSX
0.5
—
tKHARX
0.5
—
SYSCLK to output enable
tKHOE
0.5
—
ns
5
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
17