MT88E43AS View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
Manufacturer
MT88E43AS Datasheet PDF : 26 Pages
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Data Sheet
MT88E43
AC Electrical Characteristics† - 3-Wire Interface Timing
Characteristics
Sym
Min Max Units
1 PWDN Power-up time
2 OSC1 Power-down time
tPU
50
ms
tPD
1
ms
3
Input FSK to CD low delay
tCP
25
ms
4
CD Input FSK to CD high delay
tCA
8
ms
5
Hysteresis
8
ms
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Notes
AC Electrical Characteristics† - 3-Wire Interface Timing (Mode 0)
Characteristics
Sym
Min Typ‡ Max Units
Notes*
1
Rise time
tRR
200 ns
2 DR Fall time
tRF
200 ns
3
Low time
tRL
415 416 417 µs
4
Rate
DATA
5
Input FSK to DATA delay
1188 1200 1212 baud
tIDD
1
5
ms
6
Rise time
tR
200 ns
7 DATA Fall time
8 DCLK DATA to DCLK delay
tF
200 ns
tDCD
6
416
µs
9
DCLK to DATA delay
tCDD
6
416
µs
10
Frequency
fDCLK0 1201.6 1202.8 1204 Hz
11 DCLK High time
tCH
415 416 417 µs
12
Low time
tCL
415 416 417 µs
13 DCLK DCLK to DR delay
DR
tCRD
415 416 417 µs
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. FSK input data at 1200 ±12 baud.
2. OSC1 at 3.579545 MHz ±0.1%.
3. Function of signal condition.
into 50pF Load
into 50pF Load
2
1
into 50pF Load
into 50pF Load
1, 2, 3
1, 2, 3
2
2
2
2
AC Electrical Characteristics† - 3-Wire Interface Timing (Mode 1)
Characteristics
Sym
Min Max
1
Frequency
2 DCLK Duty cycle
fDCLK1
1
30
70
3
Rise time
tR1
20
4 DCLK, DCLK low set up to DR
5
DR DCLK low hold time after DR
tDDS
500
tDDH
500
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Units
MHz
%
ns
ns
ns
Notes
5-69
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