NCP1631 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
NCP1631 Datasheet PDF : 23 Pages
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NCP1631
Given the regulation low bandwidth of the PFC systems,
(VCONTROL) and then (VREGUL) are slow varying signals.
Hence, the line current absorbed by each phase is:
Iin(phase1) + Iin(phase2) + k Vin
ƪ ƫ where: k + constant +
CtVREGUL
2 L It
(eq. 6)
Hence, the input current is then proportional to the input
voltage and the ac line current is properly shaped.
One can note that this analysis is also valid for CrM
operation that is just a particular case of this functioning
where (t3=0), which leads to (t1+t2=Tsw) and
(VTON=VREGUL). That is why the NCP1631 automatically
adapts to the conditions and jumps from DCM and CrM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
The charging current It is internally processed to be
proportional to the square of the line magnitude. Its value
is however programmed by the pin 3 resistor to adjust the
available on−time as defined by the Ton1 to Ton4 parameters
of the data sheet.
From these data, we can deduce:
t1
+
Ton(ms)
+
50
n
Rt 2
Vpin7
2
(eq. 7)
From this equation, we can check that if Vpin7 (BO
voltage) is 1 V and Rt is 20 kW (Ipin3 = 50 mA) that the
on−time is 20 ms as given by parameter Ton1.
Since:
VREGUL(max) + 1.66 V
Ton
+
CtVREGUL
It
2 Ǹ2
Vpin7 +
Vin(rms)
p
k
BO
where kBO is the scale down factor of the BO sensing
network
ǒ Ǔ kBO
+
Rbo2
Rbo1 ) Rbo2
(see Brown−out section)
We can deduce the total input current value and the
average input power:
Iin(rms)
^
26.9
(Rt)2VREGUL
@ 1012 L kBO 2Vin,rms
(eq. 8)
Pin,avg
^
(Rt)2VREGUL
26.9 @ 1012 L kBO
2
(eq. 9)
Figure 6. PWM Circuit and Timing Diagram
timing capacitor
s aw −too th
PWM
comparator
+
to PWM latch
−
VREGUL
R1
OA1 Vton
+
−
C1
S3
SKIP
OV P
OF F
OC P
0. 5*
IN 1
(I se nse
− 210 m)
S1
−> V ton d u ring (t1+t2)
S2
−> 0 V d u ring t3 (d e a d −time)
−> V ton *(t1+t2)/T in average
VBOcomp
(from BO block)
DT
(high during dead−time)
pfcOK
In−rus h
The integrator OA1 amplifies the error between VREGUL and
IN1 so that in average, (VTON*(t1+t2)/Tsw) equates VREGUL.
Figure 7. VTON Processing Circuit
The “VTON processing circuit” is “informed” when there
is an OVP condition or a skip sequence, not to
over−dimension VTON in that conditions. Otherwise, an
OVP sequence or a skipped cycle would be viewed as a
“normal” dead−time phase by the circuit and VTON would
inappropriately increase to compensate it. (Refer to
Figure 7).
The output of the “VTON processing circuit” is also
grounded when the circuit is in OFF state to discharge the
capacitor C1 and initialize it for the next active phase.
Finally, the “VTON” is not allowed to be further increased
compared to VREGUL when the circuit has not completed
the start−up phase (pfcOK low) and if VBOcomp from the
brown−out block is high (refer to brown−out section for
more information).
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