AT48801 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
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AT48801 Datasheet PDF : 17 Pages
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AT48801
Interrupts (Continued)
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TFI, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier that can be configured for use as
an on-chip oscillator, as shown in Figure 7. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be
left unconnected while XTAL1 is driven, as shown in Fig-
ure 8. There are no requirements on the duty cycle of the
external clock signal, since the input to the internal clock-
ing circuitry is through a divide-by-two flip-flop, but mini-
mum and maximum voltage high and low time specifica-
tions must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware re-
set, the device normally resumes program execution from
where it left off, up to two machine cycles before the inter-
nal reset algorithm takes control. On-chip hardware inhib-
its access to internal RAM in this event, but access to the
port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when idle mode is termi-
nated by a reset, the instruction following the one that in-
vokes idle mode should not write to a port pin or to external
memory.
Power Down Mode
In the power down mode, the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-
chip RAM. The reset should not be activated before VCC
is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.
Figure 7. Oscillator Connections
Notes: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 8. External Clock Drive Configuration
Status of External Pins During Idle and Power Down
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
1-11
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