PCA9541 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
PCA9541 Datasheet PDF : 30 Pages
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Philips Semiconductors
2-to-1 I2C master selector with interrupt logic and reset
Product data sheet
PCA9541
INTERRUPT ENABLE AND CONTROL REGISTERS
DESCRIPTION
When a master seeks control of the bus by connecting its I2C
channel to the PCA9541 downstream channel, it has to write to the
Control Register (Reg#01)
Bits MYBUS and BUSON allow the master to take control of the
bus.
The MYBUS and the NMYBUS bits determine which master has
control of the bus. Tables 4 and 5 explain which master gets control
of the bus and how. There is no arbitration. Any master can take
control of the bus when it wants regardless of whether the other
master is using it or not.
The BUSON and the NBUSON bits determine whether the upstream
bus is connected or disconnected to/from the downstream bus.
Internally, the state machine does the following:
– If the combination of the BUSON and the NBUSON bits causes
the upstream to be disconnected from the downstream bus,
then that is done. So in this case, the values of the MYBUS and
the NMYBUS do not matter.
– If a master was connected to the downstream bus prior to the
disconnect, then an interrupt is sent on the respective interrupt
output in an attempt to let that master know that it is no longer
connected to the downstream bus. This is indicated by setting
the BUSLOST bit in the Interrupt Status Register.
– If the combination of the BUSON and the NBUSON bits causes
a master to be connected to the downstream bus and if there is
no change in the BUSON bits since when the disconnect took
effect, then the master requesting the bus is connected to the
downstream bus. If it requests a bus initialization sequence,
then it is performed.
– If there is no change in the combination of the BUSON and the
NBUSON bits and a new master wants the bus, then the
downstream bus is disconnected from the old master that was
using it and the new master gets control of it. Again, the bus
initialization if requested is done. The appropriate interrupt
signals are generated.
After a master has sent the bus control request:
1. The previous master is disconnected from the I2C-bus. An
interrupt to the previous master is sent through its INT line to let
it know that it lost control of the bus. BUSLOST bit in the
Interrupt Status Register is set. This interrupt can be masked by
setting the BUSLOSTMSK bit to 1.
2. A built-in bus initialization/recovery function can take temporary
control of the downstream channel to initialize the bus before
making the actual switch to the new bus master. This function is
activated by setting the BUSINIT to 1 by the master during the
same write sequence as the one programming MYBUS and
BUSON bits.
When activated and whether the bus was previously idle or not:
– 9 clock pulses are sent on the SCL_SLAVE.
– SDA_SLAVE line is released (HIGH) when the clock pulses are
sent to SCL_SLAVE. This is equivalent to sending 8 data bits
and a not acknowledge
– Finally a STOP condition is sent to the downstream slave
channel.
This sequence will complete any read transaction which was
previously in process and the downstream slave configured as a
slave-transmitter should release the SDA line because the
PCA9541 did not acknowledge the last byte.
3. When the initialization has been requested and completed, the
PCA9541 sends an interrupt to the new master through its INT
line and connects the new master to the downstream channel.
BUSINIT bit in the Interrupt Status Register is set. The switch
operation occurs after the master asking the bus control
has sent a STOP command. This interrupt can be masked by
setting the BUSINITMSK bit to 1.
4. When the bus initialization/recovery function has not been
requested (BUSINIT=0), the PCA9541 connects the new master
to the slave downstream channel. The switch operation occurs
after the master asking the bus control has sent a STOP
command. PCA9541 sends an interrupt to the new master
through its INT line if the built-in bus sensor function detects a
non-idle condition in the downstream slave channel at the
switching time. BUSOK bit in the Interrupt Status Register is set.
This means that a STOP condition has not been detected in the
previous bus communication and that an external bus
recovery/initialization must be performed. If an idle condition has
been detected at the switching time, no interrupt will be sent.
This interrupt can be masked by setting the BUSOKMSK bit to 1.
Interrupt status can be read. See paragraph INTERRUPT STATUS
REGISTER DESCRIPTION for more information.
The MYTEST and the NMYTEST bits cause the interrupt pins of the
respective masters to be activated for a ”functional interrupt test”.
NOTES:
1. The regular way to proceed is that a master asks to take the
control of the bus by programming MYBUS and BUSON bits.
Nevertheless, the same master can also decide to give up the
control of the bus and give it to the other master. This is also
done by programming the MYBUS and BUSON bits.
2. Any writes either to the Interrupt Enable Register or the Control
Register cause the respective register to be updated on the 9th
clock cycle, i.e. on the rising edge of the acknowledge clock
cycle.
3. The actual switch from one channel to another or the switching
off of both the channels happens on a STOP command.
2004 Oct 01
6
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