HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
AC Characteristics (cont’d) 1, 2
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-8
PC100-222
-8B
PC100-323
min. max. min. max.
Unit Note
Refresh Cycle
Self Refresh Exit Time
tSREX
10
Refresh Period
tREF
64
Refresh Interval
128Mbit SDRAM based modules
–
256Mbit SDRAM based modules
–
–
10
–
64
15.6 –
7.8
–
–
–
15.6
7.8
ns 9
ms 6
µs
µs
Read Cycle
Data Out Hold Time
tOH
3
–
3
–
ns 2
Data Out to Low Impedance Time tLZ
0
–
0
–
ns
Data Out to High Impedance
tHZ
3
8
3
10
ns 8
Time
DQM Data Out Disable Latency tDQZ
–
2
–
2
CLK
Write Cycle
Data Input to Precharge
(write recovery)
Data In to Active/Refresh
DQM Write Mask Latency
tWR
2
–
2
–
CLK
tDAL
5
–
5
–
CLK
tDQW
0
–
0
–
CLK
Semiconductor Group
10
1998-08-01