MC14512BCL View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
MC14512BCL Datasheet PDF : 6 Pages
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PULSE
GENERATOR
VDD
S3
S4
VSS
VDD
DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
VDD
Z
CL
1k
S1
S2
VSS
20 ns
DISABLE
INPUT
tPLZ
OUTPUT
tPHZ
OUTPUT
90%
50%
10%
10%
90%
Switch Positions for 3–State Test
Test
S1
S2
S3
S4
VSS
tPHZ Open Closed Closed Open
tPLZ Closed Open Open Closed
tPZL Closed Open Open Closed
tPZH Open Closed Closed Open
20 ns
VDD
VSS
tPZL
90% VOH
VOL
tPZH
≈ 2.5 V @ VDD = 5 V,
10 V, AND 15 V
≈ 2 V @ VDD = 5 V
VOH ≈ 6 V @ VDD = 10 V
10% VOL ≈ 10 V @ VDD = 15 V
Figure 3. 3–State AC Test Circuit and Waveform
13
C
12
B
11
A
1
X0
2
X1
3
X2
4
X3
5
X4
6
X5
7
X6
9
X7
LOGIC DIAGRAM
15
DISABLE
10
INHIBIT
VDD
14
Z
VSS
1
IN
OUT
IN
2
TRANSMISSION
GATE
1
OUT
2
SELECTED
DEVICE
MC14512B
MC14512B
DATA
BUS
IOD
IL
ITL
LOAD
ITL
MC14512B
3–STATE MODE OF OPERATION
Output terminals of several MC14512B 8–Bit Data Selec-
tors can be connected to a single date bus as shown. One
MC14512B is selected by the 3–state control, and the re-
maining devices are disabled into a high–impedance “off”
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive
current, IOD, 3–state or disable output leakage current, ITL,
and the load current, IL, required to drive the bus line (includ-
ing fanout to other device inputs), and can be calculated by:
N = IOD – IL + 1
ITL
N must be calculated for both high and low logic state of the
bus line.
MOTOROLA CMOS LOGIC DATA
MC14512B
373
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