PSD913G1-C-15M View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD913G1-C-15M

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD9XX Family

The

PSD935G2

Functional

Blocks

(cont.)

Figure 6. Priority Level of Memory and I/O Components

PSD935G2

Highest Priority

Lowest Priority

Level 1

SRAM, I/O

Level 2

Secondary Flash Memory

Level 3

Main Flash Memory

9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces

The 80C51 and compatible family of microcontrollers, can be configured to have separate

address spaces for code memory (selected using PSEN) and data memory (selected using

RD). Any of the memories within the PSD935G2 can reside in either space or both spaces.

This is controlled through manipulation of the VM register that resides in the PSD’s CSIOP

space.

The VM register is set using PSDsoft to have an initial value. It can subsequently be

changed by the microcontroller so that memory mapping can be changed on-the-fly.

For example, you may wish to have SRAM and main Flash in Data Space at boot, and

secondary Flash memory in Program Space at boot, and later swap main and secondary

Flash memory. This is easily done with the VM register by using PSDsoft to configure it for

boot up and having the microcontroller change it when desired.

Table 11 describes the VM Register.

Table 11. VM Register

Bit 7

PIO_EN

Bit 6* Bit 5* Bit 4

Bit 3

FL_Data Boot_Data

Bit 2

FL_Code

Bit 1

Bit 0

Boot_Code SRAM_Code

0 = disable *

PIO mode

* 0 = RD 0 = RD

can’t can’t

0 = PSEN 0 = PSEN 0 = PSEN

can’t

can’t

can’t

access access

access access

access

Flash Boot Flash Flash

Boot Flash SRAM

1= enable *

PIO mode

* 1 = RD 1 = RD

access access

1 = PSEN 1 = PSEN 1 = PSEN

access access

access

Flash Boot Flash Flash

Boot Flash SRAM

NOTE: Bits 6-5 are not used.

28

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