SL20T0081 View Datasheet(PDF) - System Logic Semiconductor
Part Name
Description
Manufacturer
SL20T0081 Datasheet PDF : 56 Pages
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SLS System Logic Semiconductor
SL20T0081
PAD CONFIGURATION
PAD Layout
Figure 1. SL20T0081 PAD Layout
282
283
325
1
Y
X
(0,0)
147
146
104
103
Table 2. SL20T0081 PAD Dimensions
Item
Pad No.
Chip Size
-
Size
Unit
X
Y
8900
3000
2 to10, 94 to 102, 104 to 146,
60
148 to 281, 283 to 325
11 to 41, 45-46, 50 to 93
80
Pad pitch
41-42, 44-45, 46-47, 49-50
110
42 to 44, 47 to 49
120
1-2, 102-103, 147-148, 281-282
131
µm
10-11, 93-94
90
2 to 10, 94 to 102, 148 to 281
37
92
104 to 146, 283 to 325
92
37
Bumped PAD size
11 to 41, 45, 46, 50 to 93
57
92
(Bottom)
42 to 44, 47 to 49
67
92
1, 103, 147, 282
72
97
Bumped PAD height
All PAD
18
Figure 2. Align Key Coordination
COG Align Key Coordination
30µm 30µm 30µm
30µm 30µm 30µm
ILB Align Key Coordination
60µm
Potting Mark Coordination
72µm
(-4230.0, -1415.0)
(4230.0, -1430.0)
upper left : (-4365.0, 1415.0)
lower right : (4365.0, -1415.0)
(4346.0, 1406.0)
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