RT8204A View Datasheet(PDF) - Richtek Technology
Part Name
Description
Manufacturer
RT8204A Datasheet PDF : 19 Pages
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RT8204A
MOSFET Gate Driver (UGATE, LGATE)
The high side driver is designed to drive high current, low
RDS(ON) N-MOSFETs. When configured as a floating driver,
5V bias voltage is delivered from VDDP supply. The average
drive current is proportional to the gate charge at
VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
BOOT and PHASE pins.
A dead time to prevent shoot through is internally
generated between high side MOSFET off to low side
MOSFET on, and low side MOSFET off to high side
MOSFET on.
The low side driver is designed to drive high current, low
RDS(ON) N-MOSFETs. The internal pull-down transistor that
drives LGATE low is robust, with a 0.6Ω typical on-
resistance. A 5V bias voltage is delivered form VDDP
supply. The instantaneous drive current is supplied by the
flying capacitor between VDDP and PGND.
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lead to
efficiency-killing, EMI-producing shoot-through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high-side
MOSFET without degrading the turn-off time (Figure 4).
+5V
VIN
R
BOOT
UGATE
PHASE
Figure 4. The UGATE Rise Time Reduction
Power-Good Output (PGOOD)
The power good output is an open-drain output and requires
a pull-up resistor. When the output voltage is 15% above
or 10% below its set voltage, the PGOOD gets pulled
low. It is held low until the output voltage returns to within
these tolerances once more. In soft start, the PGOOD is
actively held low and is allowed to be pulled high until soft
start is over and the output reaches 93% of its set voltage.
There is a 2.5μs delay built into the PGOOD circuitry to
prevent false transition.
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14
POR, UVLO and Soft-Start
Power-on reset (POR) occurs when VDD rises above to
approximately 4.3V, the RT8204A will reset the fault latch
and prepare the PWM for operation. If the VDD is below
4.1V (MIN), the VDD undervoltage-lockout (UVLO) circuitry
inhibits switching by keeping UGATE and LGATE low.
A built-in soft-start is used to prevent the surge current
from power supply input after EN/DEM is enabled. It
clamps the ramping of internal reference voltage which is
compared with the FB signal. The typical soft-start duration
is 1.35ms.
Furthermore, the maximum allowed current limit is
segment in 2 steps during 1.35ms period.
Output Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage protection. When the output voltage exceeds 15%
of the its setting voltage threshold, the over voltage
protection is triggered and the low side MOSFET is latched
on. This activates the low side MOSFET to discharge the
output capacitor.
The RT8204A is latched once OVP is triggered and can
only be released by VDD or EN/DEM power on reset. There
is a 20μs delay built into the over voltage protection circuit
to prevent false transitions.
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
70% of its set voltage threshold, the under voltage
protection is triggered and then both UGATE and LGATE
gate drivers are forced low. In order to remove the residual
charge on the output capacitor during the under voltage
period, if the PHASE is greater than 1V, the LGATE is
forced high until PHASE is lower than 1V. There is 2.5μs
delay built into the under voltage protection circuit to
prevent false transitions. During the soft-start, the UVP
will be blanked around 3.1ms.
Output Voltage Setting (FB)
The output voltage can be adjusted from 0.75V to 3.3V by
setting the feedback resistor R1 and R2 (Figure 5). Choose
R2 to be approximately 10kΩ, and solve for R1 using the
equation :
DS8204A-05 April 2011
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