RT9232BPS View Datasheet(PDF) - Richtek Technology
Part Name
Description
Manufacturer
RT9232BPS Datasheet PDF : 14 Pages
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RT9232B
MOSFET Selection
The selection of MOSFETs is based upon the
considerations of RDS(ON), gate driving requirements, and
thermal management requirements. The power loss of
upper MOSFET consists of conduction loss and switching
loss and is expressed as :
PUPPER = PCOND_UPPER + PSW_UPPER
(8)
=
I2OUT
×
RDS(ON)
×D
+
1
2
IOUT
× VIN × (TRISE + TFALL ) × fOSC
where TRISE and TFALL are rising and falling time of VDS of
upper MOSFET respectively. RDS(ON) and QG should be
simultaneously considered to minimize power loss of upper
MOSFET.
The power loss of lower MOSFET consists of conduction
loss, reverse recovery loss of body diode, and conduction
loss of body diode and is expressed as :
PLOWER = PCOND_LOWER + PRR + PDIODE
(9)
= I2OUT × RDS(ON) × (1- D) + QRR × VIN × fOSC
+
1
2
IOUT
×
VF
×
TDIODE
×
fOSC
where TDIODE is the conducting time of lower body diode.
Special control scheme is adopted to minimize body diode
conducting time. As a result, the RDS(ON) loss dominates
the power loss of lower MOSFET. Use MOSFET with
adequate RDS(ON) to minimize power loss and satisfy
thermal requirements.
Feedback Compensation
Figure 2 highlights the voltage-mode control loop for a
synchronous buck converter. Figure 3 shows the
corresponding Bode plot. The output voltage (VOUT) is
regulated to the reference voltage. The error amplifier EA
output (COMP) is compared with the oscillator (OSC)
sawtooth wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (L and COUT).
The modulator transfer function is the small-signal transfer
function of VOUT/COMP. This function is dominated by a
DC gain and the output filter (L and COUT), with a double
pole break frequency at FP_LC and a zero at FZ_ESR. The
DC gain of the modulator is simply the input voltage (VIN)
divided by the peak-to-peak oscillator voltage ΔVOSC.
The break frequency FLC and FESR are expressed as
Equation (10) and (11) respectively.
FP_LC =
1
(10)
2π LCOUT
FZ_ESR
=
2π
1
× ESR × COUT
(11)
The compensation network consists of the error amplifier
EA and the impedance networks ZIN and ZFB. The goal of
the compensation network is to provide a closed loop
transfer function with the highest DC gain, the highest
0dB crossing frequency (FC) and adequate phase margin.
Typically, FC in range 1/5~1/10 of switching frequency is
adequate. The higher FC is, the faster dynamic response
is. A phase margin in the range of 45°C~ 60°C is desirable.
The equations below relate the compensation network’s
poles, zeros and gain to the components (R1, R2, R3,
C1, C2, and C3) in Figure 2.
FZ1
=
2π
1
× R2 × C1
(12)
FZ2
=
2π
1
× (R1+ R3) × C3
(13)
FP1
=
2π
1
×
R2
×
C1×
C1+
C2
C2
(14)
FP2
=
2π
1
× R3 × C3
(15)
OSC
PWM
Comparator
-
ΔVOSC
+
VIN
Driver
Driver
L
PHASE
COUT
VOUT
ZFB
VE/A
-
EA+
ZIN
REF
ESR
C2
ZFB
C1 R2 C3
ZIN VOUT
R3
COMP
R1
-
FB
EA+
REF
Figure 2
www.richtek.com
12
DS9232B-03 March 2007
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