RV5VE0×××
• Formula for calculating Reset Delay Time is
tD = 0.69 × RD × CD
wherein RD is the resistance of a built-in resistor and can be set at 1MΩ in IC, so that the above formula is:
tD = 0.69 × 106× CD
Voltage Detector with Delay Circuit is constructed as shown below.
• Block Diagram of Voltage Detector with delay Circuit.
VSEN2
Current Source
RD
+
–
Vref
CD
Extermal Capacitor
VDD
RESET
GND
5. Main Power Source Control (in the case of Optional Mask Version)
• This IC includes built-in Edge Trigger Flip-Flop (Rising Edge Operation) and AND Gate, so that Main Power
Source of any instruments can be turned ON/OFF by “AND” of Toggle Input and Level Input.
• Edge Trigger Flip-Flop is reset by One Shot Pulse Generator when Voltage Detector 1 or 2 detects the lowering
of the voltage. This Flip-Flop can be continuously reset during the detection.
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