C161U View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

C161U

Embedded C166 with USB,USART and SSC

Infineon Technologies 

C161U

Pin Descriptions

Table 2

Microprocessor Bus and Control Signals (cont’d)

Pin No.

Symbol Input (I)

Function

Output (O)

84-87, 90-92 P6.0-

O

P6.3,

I/O

P6.5-

P6.7

O

...

O

I

O

O

Port6 is an 7-bit bidirectional I/O port. It is bit-

wise programmable for input or output via

direction bits. For a pin configured as input, the

output driver is put into high-impedance state.

Port6 outputs can be configured as push/pull

or open-drain drivers.

P6.0 CS0

Chip Select 0 Output

...

...

...

P6.3 CS3

Chip Select 3 Output

P6.5 HOLD External Master Hold

Request Input

P6.6 HLDA Hold Acknowledge Output

P6.7 BREQ Bus Request Output

97-98

P2.0-

I/O

P2.1

I

I

PORT2 is an 2-bit bidirectional I/O port. It is

bit-wise programmable for input or output via

direction bits. For a pin configured as input, the

output driver is put into high-impedance state.

Port2 outputs can be configured as push/pull

or open-drain drivers.

P2.0 EX0IN

Fast External Interrupt 0

Input

P2.1 EX1IN

Fast External Interrupt 1

Input

34

RD

O

External Memory Read Strobe. RD is

activated for every external instruction or data

read access.

35

WR/WRL O

External Memory Write Strobe. In WR mode

this pin is activated for every external data

write access. In WRL mode this pin is

activated for low byte data write accesses on a

16-bit bus, and for every data write access on

an 8-bit bus. See WRCFG in register

SYSCON for mode selection.

37

ALE

O

Address Latch Enable Output. Can be used for

latching the address into external memory or

an address latch in the multiplexed bus

modes.

Data Sheet

20

2001-04-19

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