SC4810B/E
POWER MANAGEMENT
Application Information (Cont.)
output voltage ripple. The designer needs to take the
output inductance and output capacitance and the ESL
and ESR of the output capacitor into consideration during
the design.
For this application, one Panasonic power choke output
inductor was selected and three 6.3V, 100uF TDK
ceramic capacitors were adopted in the design.
Selection of the Current Sensing Resistor
The selection of the current sensing resistor is based on
the over-current protection triggering point. SC4810
employs a Hiccup mode over-current protection with an
overcurrent threshold of 600mV. A voltage signal above
600mV on the CS pin will trigger hiccup mode overcurrent
protection. Suppose the over-current protection setpoint
is set to be Iov. The threshold voltage of SC4810 is
Vthreshold. The turns ratio of the power transformer is
Ns/Np. The turns ratio of the current sensing transformer
is Ncs:1. Then the Rsense would be calculated as:
Rsense
=
VThreshold × NP × NCS
IOV × NS
......(1)
VRCT
3V
0V
Fig.4 Voltage Waveform on RCT Pin
VPK
t
As illustrated, the capacitor C is charged via the resistor
R from VREF. Whenever the voltage on the RCT pin
reaches 3V, the capacitor C will be discharged through
an internal FET shorted to ground. When the clock signal
circuit is connected as in Fig.3, the frequency of the clock
signal is defined, as in equation 2.
F=
1
........(2)
−
(RT
+ 1k)
•
CT
•
ln
1 −
VP−K
VREF
V is the reference voltage of the SC4810, 4V for
REF
SC4810A/D and 5V for SC4810B/C/E.
In this application, to get 600kHz, C = 180pF,
(R + 1k) = 10k ohms and VP-K = 3V.
Set Clock Frequency
Maximum Duty Ratio Limit
The SC4810 uses a pair of resistors and capacitors to
generate a triangle signal as the clock signal, as illustrated
in Fig. 3.
SC4810 features maximum duty ratio limitation for ex-
tra protection. The maximum duty ratio is determined by
the voltage on DMAX pin. As illustrated as in Fig. 5, VDMAX
will be compared with VRCT and DMAX is determined by
the comparison of the two signals.
VRCT
RCT
C
R
VREF
Fig. 3 Configuration for Clock Signal
The voltage waveform on the RCT pin is illustrated as in
Fig. 4.
2006 Semtech Corp.
11
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