SYNCOAM Co., Ltd.
SEPS225
Version: 0.8
5) Clock Synchronized Serial Interface (SPI)
Setting PS pin to the “0” level allows clock synchronized serial data(SPI) transfer, using the chip select
pin(CSB), RS pin, serial transfer clock pin(SCL) and serial data input(SDI).
When chip is not selected, internal shift register and counter is resets to initial value. Input data through SDI
pin are latched at the rising edge of serial transfer clock(SCL). SDI inputs are converted to 16‐bit or 18‐bit
data and transferred to memory at the 16th/18th rising edge serial clock, respectively.
Serial data input(SDI) is identified to display data or command by RS pin.
RS
Function
L
Command
H
Parameter/ Data
after 8‐bit data transfer, serial transfer clock(SCL) goes to “H” at the non‐access period. SDI and SCL signals
are sensitive to external noise. To prevent miss operation chip selector state should be released(CSB = “H”)
after 8‐bit data transfer as shown in the following.
*Note : When the SPI mode is selected, DB[15] pin must be unconnected.
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