VDD Over-voltage Protection (OVP)
VDD over-voltage protection has been built in to prevent
damage due to abnormal conditions. Once the VDD
voltage is over the VDD over-voltage protection voltage
(VDD-OVP) and lasts for tD-VDDOVP, the PWM pulses are
disabled until the VDD voltage drops below the UVLO,
then starts again. Over-voltage conditions are usually
caused by open feedback loops.
Limited Power Control
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
tD-OLP, PWM output is turned off. As PWM output is
turned off, the supply voltage VDD begins decreasing.
When VDD goes below the turn-off threshold (~10.5V)
the controller is totally shut down. VDD is charged up to
the turn-on threshold voltage of 16V through the startup
resistor until PWM output is restarted. This protection
feature continues as long as the overloading condition
persists. This prevents the power supply from
overheating due to overloading conditions.
Noise Immunity
Noise on the current sense or control signal may cause
significant pulse-width jitter, particularly in continuous-
conduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the SG6741A, and increasing the
power MOS gate resistance improve performance.
© 2008 Fairchild Semiconductor Corporation
SG6741A • Rev. 1.0.1
9
www.fairchildsemi.com