HD6437065A View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

HD6437065A

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7000 Series

Renesas Electronics 

Appendix D Restrictions and Caution on HD64F7065S (and HD64F7065A Lots Prior to “1D5”)

D.3 Pin State Related Restrictions

The states of pins PF7 and PF6 in software standby mode are as follows.

1. PF7 has PF7/IRQOUT/TIOC0D functions. It goes to the high-impedance state in software

standby mode, regardless of which function is selected.

2. PF6 has PF6/TxD1/TIOC2A functions. This pin, too, basically goes to the high-impedance

state in software standby mode, as with the PF7 pin. However, when the PF6 output function

or TxD1 output function is selected and the pin state is high-level output, the high-level output

state is retained when a transition is made to software standby mode.

D.4 Caution Concerning Electrical Characteristics

In external space access, noise with a peak value of 1.5 V max. may occur while the write signal

(WR) is low.

D.5 DMAC Restrictions

The DMA transfer overrun may occur when using the four on-chip DMAC channels (channel 0 to

channel 3).

In external request mode and on-chip peripheral module request mode, once DMA transfer is

executed, DMA transfer may continue to be executed until the contents of DMAC transfer count

register (DMATCRn) and next transfer count register (NDMATCRn) become 0. This does not

apply to auto request mode.

Conditions under which the DMAC stops for certain are shown below:

• When chain transfer is not performed (chain transfer enable bit (CHNE) = 0): until DMATCRn

=0

• When chain transfer is performed (chain transfer enable bit (CHNE) = 1): until DMATCRn = 0

and NDMATCRn = 0

There are some restrictions about TEND output. Refer to 9.6 DMAC Restrictions.

Rev. 5.00 Sep 11, 2006 page 911 of 916

REJ09B0332-0500

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