Si3050 + Si3018/19
4. AOUT PWM Output
Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3050
for call progress monitoring purposes.To enable this mode, the INTE bit (Register 2) should be set to 0, the PWME
bit (Register 1) set to 1, and the PWMM bits (Register 2) set to 00.
+5VA
LS1
AOUT
R41
Q6
C41
Figure 18. AOUT PWM Circuit for Call Progress
Table 12. Component Values—AOUT PWM
Component
LS1
Q6
C41
R41
Value
Speaker BRT1209PF-06
NPN KSP13
0.1 µF, 16 V, X7R, ±20%
150 1/10 W, ±5%
Supplier
Intervox
Fairchild
Venkel, SMEC
Venkel, SMEC, Panasonic
Registers 20 and 21 allow the receive and transmit paths to be attenuated linearly. When these registers are set to
all 0s, the transmit and receive paths are muted. These registers affect the call progress output only and do not
affect transmit and receive operations on the telephone line.
The PWMM[1:0] bits (Register 1, bits 5:4) select one of three different PWM output modes for the AOUT signal,
including a delta-sigma data stream, a 32 kHz return to 0 PWM output, and a balanced 32 kHz PWM output.
Rev. 1.31
19