ST7577 View Datasheet(PDF) - Sitronix Technology Co., Ltd.
Part Name
Description
Manufacturer
ST7577 Datasheet PDF : 48 Pages
| |||
ST7577
CONFIGURATION PIN
Data format (MSB on top or LSB on top).
MLB
I
MLB=”H”, MSB on top (D7 on top);
1
MLB=”L”, LSB on top (D0 on top).
Duty selection pin. Please refer to Page11 for detail output Map.
DTY
I
DTY=”L”, 1/39 duty;
1
DTY=”H”, 1/12 duty.
Set power mode. This pin will change the V0 (Vop) formula parameter.
PM
I
V0=( a + VOP[6:0] x b )
PM=”L”, a=3.0V, b=0.03V;
1
PM=”H”, a=4.5V, b=0.03V.
Select MPU interface Port-A (left side) or Port-B (right side).
MODE
I
MODE=”L”, use Port-A (Port-B should be floating).
1
MODE=”H”, use Port-B (Port-A should be floating).
TEST PIN
T0~T8 left them open.
T0~T9
Test
10
T9 must connect to VDD.
l ST7577 has 2 sets of interface port (Port-A & Port-B). These two ports can be selected by “MODE” pin.
Port-A and Port-B are identical (CSB, A0, /RW, /RD, D7~D0) except RESB pin.
l The unused pins should be left floating.
l The Microprocessor Interface pins should not be left floating under any operation mode.
Recommend I/O pins ITO Resistance Limitation
Pin Name
VRS, T[8:0]
VSS
VDD
VDD2
V0 (V0I + V0O + V0S), XV0 (XV0I + XV0O + XV0S), VG (VGI + VGO + VGS), VM
CSB, A0, /RD, /WR, D[7:0]
PS[2:0], OSC*1, MLB, DTY, MODE, T9
RESB
ITO Resistance
Floating
<100Ω
<100Ω
<100Ω
<500Ω
<1KΩ
<5KΩ
<10KΩ
Notes:
1. If using internal clock, OSC is connect to VDD and the limitation of ITO resistance will be “No Limitation”.
If using external clock, the ITO resistance of OSC should be kept lower than 500Ω to keep the clock signal quality.
Ver 1.0a
11/48
2008/02/14
Share Link: 