ST8009
(Segment Mode 2)
(VSS = 0 V, VDD = +5.0±0.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 to +85 °C)
PARAMETER
SYMBOL CONDITIONS
MIN. TYP. MAX. UNIT
Shift clock period
tWCK
tR,tF ≤ 10ns
66
ns
Shift clock "H" pulse width
tWCKH
23
ns
Shift clock "L” pulse width
tWCKL
23
ns
Data setup time
tDS
15
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
50
ns
Latch pulse rise to shift clock rise time
tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Latch pulse fall to shift clock rise time
tLSW
50
ns
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
Input signal fall time
tF
50
ns
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
41
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTE
1
2
2
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
V1.1
36/43
2006/11/1